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M48Z128 M48Z128Y, M48Z128V
5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER(R) SRAM
Features

Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation; unlimited WRITE cycles 10 years of data retention in the absence of power Battery internally isolated until power is first applied Automatic power-fail chip deselect and WRITE protection WRITE protect voltages: (VPFD = power-fail deselect voltage) - M48Z128: VCC = 4.75 to 5.5 V 4.5 V VPFD 4.75 V - M48Z128Y: VCC = 4.5 to 5.5 V 4.2 V VPFD 4.5 V - M48Z128V: VCC = 3.0 to 3.6 V 2.8 V VPFD 3.0 V (contact ST sales office for availability) Pin and function compatible with JEDEC standard 128 K x 8 SRAMs RoHS compliant - Lead-free second level interconnect
32 1
PMDIP32 module (PM)

July 2010
Doc ID 2426 Rev 5
1/20
www.st.com 1
Contents
M48Z128, M48Z128Y, M48Z128V
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PMDIP32 - 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of figures
M48Z128, M48Z128Y, M48Z128V
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8 Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PMDIP32 - 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M48Z128, M48Z128Y, M48Z128V
Description
1
Description
The M48Z128/Y/V ZEROPOWER(R) RAM is a 128 Kbit x 8 non-volatile static RAM organized as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated batterybacked memory solution. The M48Z128/Y/V is a non-volatile pin and function equivalent to any JEDEC standard 128 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP module houses the M48Z128/Y/V silicon with a long-life lithium button cell in a single package. Figure 1. Logic diagram
VCC
17 A0-A16 M48Z128 M48Z128Y M48Z128V
8 DQ0-DQ7
W E G
VSS
AI01194
Table 1.
Signal names
A0-A16 DQ0-DQ7 E G W VCC VSS NC Address inputs Data inputs / outputs Chip enable input Output enable input WRITE enable input Supply voltage Ground Not connected internally
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Description Figure 2. DIP connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 2 31 30 3 29 4 28 5 27 6 26 7 8 M48Z128 25 M48Z128Y 24 9 M48Z128V 23 10 22 11 21 12 20 13 14 19 15 18 17 16
M48Z128, M48Z128Y, M48Z128V
VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI01195
Figure 3.
Block diagram
VCC A0-A16
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
131,072 x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI01196
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M48Z128, M48Z128Y, M48Z128V
Operating modes
2
Operating modes
The M48Z128/Y/V also has its own power-fail detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect
Operating modes
VCC 4.75 to 5.5 V or 4.5 to 5.5 V or 3.0 to 3.6 V VSO to VPFD (min)(1) VSO(1) E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery backup mode
1. See Table 10 on page 15 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage.
2.1
READ mode
The M48Z128/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 1,048,576 locations in the static storage array. Thus, the unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G (output enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain low, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access.
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Operating modes Figure 4.
M48Z128, M48Z128Y, M48Z128V Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7
VALID tAXQX tEHQZ
tGHQZ
DATA OUT
AI01197
Note:
WRITE enable (W) = high. Figure 5. Address controlled, READ mode AC waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI01078
Note:
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high. Table 3. READ mode AC characteristics
M48Z128/Y M48Z128/Y/V M48Z128/Y/V Symbol Parameter(1) -70 Min tAVAV tAVQV tELQV tGLQV READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid 5 3 30 20 5 5 70 70 70 35 5 3 35 25 10 Max Min 85 85 85 45 5 3 45 35 -85 Max -120 Min 120 120 120 60 Max ns ns ns ns ns ns ns ns ns Unit
tELQX(2) Chip enable low to output transition tGLQX(2) Output enable low to output transition tEHQZ(2) tGHQZ(2) tAXQX Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF.
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M48Z128, M48Z128Y, M48Z128V
Operating modes
2.2
WRITE mode
The M48Z128/Y/V is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX or tEHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. WRITE enable controlled, WRITE AC waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01198
tWHAX
tWHQX
Note:
Output enable (G) = high. Figure 7. Chip enable controlled, WRITE AC waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01199
tELEH
tEHAX
Note:
Output enable (G) = high.
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Operating modes Table 4. WRITE mode AC characteristics
M48Z128/Y Symbol Parameter(1) -70 Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX(2)(3) WRITE cycle time Address valid to WRITE enable Low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition 65 65 5 70 0 0 55 55 5 15 30 30 0 10 25 Max
M48Z128, M48Z128Y, M48Z128V
M48Z128/Y/V -85 Min 85 0 0 65 75 5 15 35 35 0 10 30 75 75 5 Max
M48Z128/Y/V -120 Min 120 0 0 85 100 5 15 45 45 0 10 40 100 100 5 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z128/Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "Don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z128/Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on battery storage life refer to the application note AN1012.
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M48Z128, M48Z128Y, M48Z128V
Operating modes
2.4
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (see Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface-mount). Figure 8. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
Doc ID 2426 Rev 5
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Maximum ratings
M48Z128, M48Z128Y, M48Z128V
3
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol TA TSTG TBIAS TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Temperature under bias Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation M48Z128/Y M48Z128V Value 0 to 70 -40 to 85 -10 to 70 260 -0.3 to 7 -0.3 to 7.0 -0.3 to 4.6 20 1 Unit C C C C V V V mA W
1. Soldering temperature of the IC leads is to not exceed 260 C for 10 seconds. In order to protect the lithium battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 C. Furthermore, the devices shall not be exposed to IR reflow.
Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode.
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M48Z128, M48Z128Y, M48Z128V
DC and AC parameters
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48Z128/Y 4.75 to 5.5 V or 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48Z128V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC measurement load circuit
650
DEVICE UNDER TEST
CL = 100pF or 50pF(1)
1.75V
CL includes JIG capacitance
AI03630
1. 50 pF for M48Z128V (3.3 V).
Table 7.
Symbol CIN CIO(3)
Capacitance
Parameter(1)(2) Input capacitance Input / output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5 V (M48Z128/Y) or 3.3 V (M48Z128V); sampled only, not 100% tested. 2. At 25 C, f = 1 MHz. 3. Outputs deselected.
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DC and AC parameters Table 8. DC characteristics
M48Z128, M48Z128Y, M48Z128V
M48Z128/Y Sym Parameter Test condition(1) -70 / -85 / -120 Min ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage IOL = 2.1 mA IOH = -1 mA 2.4 0 V VIN VCC 0 V VOUT VCC E = VIL Outputs open E = VIH E = VCC - 0.2 V -0.3 2.2 Max 1 1 105 7 4 0.8 VCC + 0.3 0.4
M48Z128V -85 / -120 Min Max 1 1 50 4 3 -0.3 2.2 0.6 VCC + 0.3 0.4 2.2 A A mA mA mA V V V V Unit
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. Outputs deselected.
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M48Z128, M48Z128Y, M48Z128V Figure 10. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
DC and AC parameters
tDR tRB
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
Table 9.
Symbol tF(2) tFB(3) tR tRB tWP tER
Power down/up AC characteristics
Parameter(1) VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time Write protect time E recovery time M48Z128/Y M48Z128V M48Z128/Y M48Z128V Min 300 10 150 10 1 40 40 40 150 250 120 Max Unit s s s s s ms
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Symbol
Power down/up trip points DC characteristics
Parameter(1)(2) M48Z128 Min 4.5 4.2 2.8 Typ 4.6 4.3 2.9 3.0 2.5 10 Max 4.75 4.5 3.0 Unit V V V V V YEARS
VPFD
Power-fail deselect voltage
M48Z128Y M48Z128V
VSO tDR(3)
Battery backup switchover voltage Expected data retention time
M48Z128/Y M48Z128V
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 3. At 25 C; VCC = 0 V.
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Package mechanical data
M48Z128, M48Z128Y, M48Z128V
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 11. PMDIP32 - 32-pin plastic DIP module, package outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note:
Drawing is not to scale. Table 11.
Symb Typ A A1 B C D E e1 e3 eA L S N 38.1 14.99 3.05 1.91 32 16.00 3.81 2.79 Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 1.5 0.590 0.120 0.075 32 0.630 0.150 0.110 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 Max 0.375 - 0.023 0.013 1.700 0.740 0.110
PMDIP32 - 32-pin plastic DIP module, package mechanical data
mm inches
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M48Z128, M48Z128Y, M48Z128V
Part numbering
6
Part numbering
Table 12.
Example:
Ordering information scheme
M48Z 128Y -70 PM 1
Device type M48Z
Supply voltage and write protect voltage 128 = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V 128Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 128V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V
Speed -70 = 70 ns (for M48Z128/Y) -85 = 85 ns (for M48Z128/Y/V) -120 = 120 ns (for M48Z128/Y/V)
Package PM = PMDIP32
Temperature range 1 = 0 to 70 C
Shipping method blank = ECOPACK(R) package, tubes
1. Contact local ST sales office for availability
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Environmental information
M48Z128, M48Z128Y, M48Z128V
7
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
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M48Z128, M48Z128Y, M48Z128V
Revision history
8
Revision history
Table 13.
Date May-1999 13-Apr-2000 20-Jun-2000 19-Jul-2000 14-Sep-2001 07-Nov-2001 20-May-2002 18-Nov-2002 17-Sep-2003 22-Feb-2005
Revision history
Revision 1 2 2.1 2.2 3 3.1 3.2 3.3 3.4 4 First issue Document layout changed; surface-mount chip set solution added tGLQX changed (Table 3) M48Z128V added Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10) Remove chipset option from ordering Information (Table 12) Modify reflow time and temperature footnotes (Table 5) Modifying SMT solution text (Figure 2, 4;Table 2) Remove references to M68ZXXX (obsolete) parts (Figure 4; Table 2); update disclaimer Reformatted; IR reflow, SO package updates (Table 5) Reformatted document; updated Features, Section 3: Maximum ratings, Table 11, 12; added ECOPACK(R) text to Section 5; added Section 7: Environmental information; removed SOH28, SNAPHAT(R) housing and all references from datasheet. Changes
20-Jul-2010
5
Doc ID 2426 Rev 5
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M48Z128, M48Z128Y, M48Z128V
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Doc ID 2426 Rev 5

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